? semiconductor components industries, llc, 2003 november, 2003 ? rev. 3 575 publication order number: nthc5513/d complementary, 20 v, +3.1 a / ? 2.1 a, chipfet features ? complementary n channel and p channel mosfet ? small size, 40% smaller than tsop ? 6 package ? leadless smd package featuring complementary pair ? chipfet package provides great thermal characteristics similar to larger packages ? low r ds(on) in a chipfet package for high efficiency performance ? low profile (< 1.10 mm) allows placement in extremely thin environments such as portable electronics applications ? load switch applications requiring level shift ? dc ? to ? dc conversion circuits ? drive small brushless dc motors ? designed for power management applications in portable, battery powered products maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 20 v gate ? to ? source voltage v gs 12 v continuous drain current (note 1) n ? ch steady t a = 25 c i d 3.1 a c urrent ( note 1 ) s teady state t a = 85 c 2.15 p ? ch steady t a = 25 c ? 2.1 s teady state t a = 85 c ? 1.5 pulsed drain current (note 1) n ? ch t = 10 s i dm 10 a (note 1) p ? ch t = 10 s ? 7.0 power dissipation ? steady state (note 1) t a = 25 c p d 1.1 w operating junction and storage temperature t j , t stg ? 55 to 150 c lead temperature for soldering purposes (1/8? from case for 10 seconds) t l 260 c thermal resistance ratings parameter symbol max unit junction ? to ? ambient steady ? state (note 1) r ja 110 c/w 1. surface ? mounted on fr4 board using 1 in sq. pad size (cu area = 1.127 in sq. [1 oz] including traces). g d s n ? channel mosfet 1 1 1 g d 2 2 p ? channel mosfet s 2 device package shipping ordering information NTHC5513T1 chipfet 3000/tape & reel chipfet case 1206a style 2 1 2 3 4 5 6 7 8 pin connections marking diagram c1 c1 = specific device code 1 2 3 4 8 7 6 5 s 1 g 1 s 2 g 2 d 1 d 1 d 2 d 2 bottom view top view n ? channel 20 v p ? channel ? 20 v 80 m @ 2.5 v 60 m @ 4.5 v 130 m @ ? 4.5 v 200 m @ ? 2.5 v r ds(on) typ 3.1 a ? 2.1 a i d max v (br)dss NTHC5513T1g chipfet (pb ? free) 3000/tape & reel http://onsemi.com
nthc5513 http://onsemi.com 576 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol n/p test conditions min typ max unit off characteristics (note 2) drain ? to ? source breakdown voltage v (br)dss n v gs 0 v i d = 250 a 20 v ()ss p v gs = 0 v i d = ? 250 a ? 20 zero gate voltage drain current i dss n v gs = 0 v, v ds = 16 v 1.0 a ss p v gs = 0 v, v ds = ? 16 v ? 1.0 n v gs = 0 v, v ds = 16 v, t j = 85 c 5 p v gs = 0 v, v ds = ? 16 v, t j = 85 c ? 5 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 12 v 100 na on characteristics (note 2) gate threshold voltage v gs(th) n v gs v ds i d = 250 a 0.6 1.2 v gs( ) p v gs = v ds i d = ? 250 a ? 0.6 ? 1.2 drain ? to ? source on resistance r ds (on) n v gs = 4.5 v , i d = 3.1 a 0.058 0.080 s p v gs = ? 4.5 v , i d = ? 2.1 a 0.130 0.155 p v gs = ? 2.5 v, i d = ? 1.7 a 0.200 0.240 forward transconductance g fs n v ds = 10 v, i d = 3.0 a 6.0 s s p v ds = ? 10 v , i d = ? 2.1 a 6.0 charges and capacitances input capacitance c iss n v ds = 10 v 180 pf ss p v ds = ? 10 v 185 output capacitance c oss n f 1 mhz v gs 0 v v ds = 10 v 80 oss p f = 1 mhz, v gs = 0 v v ds = ? 10 v 95 reverse transfer capacitance c rss n v ds = 10 v 25 ss p v ds = ? 10 v 30 total gate charge q g(tot) n v gs = 4.5 v, v ds = 10 v, i d = 3.1 a 2.6 4.0 nc g( o ) p v gs = ? 4.5 v, v ds = ? 10 v, i d = ? 2.1 a 3.0 6.0 gate ? to ? source gate charge q gs n v gs = 4.5 v, v ds = 10 v, i d = 3.1 a 0.6 gs p v gs = ? 4.5 v, v ds = ? 10 v, i d = ? 2.1 a 0.5 gate ? to ? drain ?miller? charge q gd n v gs = 4.5 v, v ds = 10 v, i d = 3.1 a 0.7 g p v gs = ? 4.5 v, v ds = ? 10 v, i d = ? 2.1 a 0.9 notes: 2. pulse test: pulse width 250 s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperatures.
nthc5513 http://onsemi.com 577 electrical characteristics (t j = 25 c unless otherwise noted) parameter unit max typ min test conditions n/p symbol switching characteristics (note 3) turn ? on delay time t d(on) 5.0 10 ns rise time t r n v dd = 16 v, v gs = 4.5 v, i d = 3.1 a, 9.0 18 turn ? off delay time t d(off) n v dd = 16 v , v gs = 4 . 5 v , i d = 3 . 1 a , r g = 2.5 10 20 fall time t f 3.0 6.0 turn ? on delay time t d(on) 7.0 12 rise time t r p v dd = ? 16 v, v gs = ? 4.5 v, i d = ? 2.1 a, 13 25 turn ? off delay time t d(off) p v dd = ? 16 v , v gs = ? 4 . 5 v , i d = ? 2 . 1 a , r g = 2.5 33 50 fall time t f 27 40 drain ? source diode characteristics forward diode voltage (note 2)5 v sd n v gs 0 v i s = 3.1 a 0.8 1.15 v s p v gs = 0 v i s = ? 2.1 a ? 0.8 ? 1.15 reverse recovery time (note 3) t rr n i s = 1.5 a 12.5 ns p i s = ? 1.5 a 32 charge time t a n i s = 1.5 a 9.0 a p v gs = 0 v, i s = ? 1.5 a 10 discharge time t b n v gs = 0 v , di s / dt = 100 a/ s i s = 1.5 a 3.5 b p i s = ? 1.5 a 22 reverse recovery charge q rr n i s = 1.5 a 6.0 nc p i s = ? 1.5 a 15 notes: 2. pulse test: pulse width 250 s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperatures.
nthc5513 http://onsemi.com 578 typical n ? channel performance curves (t j = 25 c unless otherwise noted) 2 v 100 c 0 8 5 6 6 3 2 v ds , drain ? to ? source voltage (volts) i d, drain current (amps) 4 2 0 1 figure 1. on ? region characteristics 0 8 2 1.5 2.5 6 4 2 1 0 3 figure 2. transfer characteristics v gs , gate ? to ? source voltage (volts) 35 0.1 0.05 0 figure 3. on ? resistance vs. gate ? to ? source voltage v gs , gate ? to ? source voltage (volts) r ds(on), drain ? to ? source resist ance ( ) i d, drain current (amps) 17 figure 4. on ? resistance vs. drain current and gate voltage i d, drain current (amps) ? 50 0 ? 25 25 1.5 1.3 1.1 0.9 0.7 50 125 100 figure 5. on ? resistance variation with temperature t j , junction temperature ( c) t j = 25 c 0.15 24 t c = ? 55 c i d = 2.7 a t j = 25 c 0.1 0.04 75 150 t j = 25 c i d = 2.7 a v gs = 4.5 v r ds(on), drain ? to ? source resistance (normalized) 4 25 c r ds(on), drain ? to ? source resist ance ( ) 1.7 v gs = 4.5 v 16 24 8 1 20 16 figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (volts) 12 v gs = 0 v i dss , leakage (na) t j = 100 c 1.4 v 1.6 v 1.8 v v gs = 2.5 v 10 100 78 2.2 v v ds 10 v 35 0.07 610 18 14 v gs = 2.4 v v gs = 5 v to 3 v 910 0.5 0
nthc5513 http://onsemi.com 579 typical n ? channel performance curves (t j = 25 c unless otherwise noted) v ds = 0 v v gs = 0 v 5 10 10 400 300 200 100 0 20 gate ? to ? source or drain ? to ? source voltage (volts) figure 7. capacitance variation c, capacitance (pf) figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge q g , total gate charge (nc) v gs, gate ? to ? source voltage (volts) t j = 25 c c oss c iss c rss v ds, drain ? to ? source voltage (volts) 10 1 10 1 100 r g , gate resistance (ohms) figure 9. resistive switching time variation vs. gate resistance t, time (ns) v dd = 16 v i d = 2.7 a v gs = 4.5 v 100 50 t d(off) t d(on) t f t r v gs v ds 15 0.9 3 0 v sd , source ? to ? drain voltage (volts) figure 10. diode forward voltage vs. current i s , source current (amps) v gs = 0 v t j = 25 c 7 0.75 0.45 0.3 1 4 2 1.2 0.6 1.05 5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 0 4 8 12 16 20 i d = 2.7 a t j = 25 c q g q gd q gs
nthc5513 http://onsemi.com 580 typical p ? channel performance curves (t j = 25 c unless otherwise noted) ? 2 v 100 c 0 4 5 3 6 3 2 ? v ds , drain ? to ? source voltage (volts) ? i d, drain current (amps) 2 1 0 1 figure 11. on ? region characteristics 0.5 4 2 1.5 2.5 3 2 1 1 0 3 figure 12. transfer characteristics ? v gs , gate ? to ? source voltage (volts) 0.1 35 0.3 0.2 0 figure 13. on ? resistance vs. gate ? to ? source voltage ? v gs , gate ? to ? source voltage (volts) r ds(on), drain ? to ? source resistance ( ) ? i d, drain current (amps) figure 14. on ? resistance vs. drain current and gate voltage ? i d, drain current (amps) ? 50 0 ? 25 25 1.4 1.2 1 0.8 0.6 50 125 100 figure 15. on ? resistance variation with temperature ? t j , junction temperature ( c) t j = 25 c 0.5 24 t c = ? 55 c i d = ? 2.1 a t j = 25 c 75 150 i d = ? 2.1 a v gs = ? 4.5 v r ds(on), drain ? to ? source resistance (normalized) 4 25 c r ds(on), drain ? to ? source resistance ( ) 1.6 ? 1.2 v 16 24 8 10 20 16 figure 16. drain ? to ? source leakage current vs. voltage ? v ds , drain ? to ? source voltage (volts) 12 v gs = 0 v ? i dss , leakage (a) t j = 150 c t j = 100 c ? 1.4 v ? 1.6 v ? 1.8 v 100 1000 10000 78 ? 2.2 v v ds ? 10 v 0.4 610 18 14 v gs = ? 2.4 v v gs = ? 6 v to ? 3 v 0.1 0.125 0.15 0.175 0.2 0.225 0.25 0.5 1.5 2.5 3.5 t j = 25 c v gs = ? 4.5 v v gs = ? 2.5 v
nthc5513 http://onsemi.com 581 v ds = 0 v v gs = 0 v 5 10 10 600 300 200 100 0 20 gate ? to ? source or drain ? to ? source voltage (volts) figure 17. capacitance variation c, capacitance (pf) figure 18. gate ? to ? source and drain ? to ? source voltage vs. total charge t j = 25 c c oss c iss c rss 500 r g , gate resistance (ohms) figure 19. resistive switching time variation vs. gate resistance t, time (ns) 50 400 ? v gs ? v ds 15 0.9 0.5 0 ? v sd , source ? to ? drain voltage (volts) figure 20. diode forward voltage vs. current ? i s , source current (amps) v gs = 0 v t j = 25 c 2.5 0.7 0.5 0.3 1 1.5 2 typical p ? channel performance curves (t j = 25 c unless otherwise noted) 0 1 2 3 4 5 01234 0 3 6 9 12 15 ? v gs ? v gs, gate ? to ? source voltage (v) i d = ? 2.1 a t j = 25 c ? v ds, drain ? to ? source voltage (v) q gd q gs ? v ds qt q g , total gate charge (nc) 1 10 100 1000 1 10 100 v dd = ? 16 v i d = ? 2.1 a v gs = ? 4.5 v t d(off) t d(on) t f t r figure 21. thermal response typical performance curves (t j = 25 c unless otherwise noted) 2 1 0.1 0.01 10 10 10 ? 4 ? 3 ? 2 ? 1 10 1 10 100 600 square wave pulse duration (sec) normalized effective transient thermal impedance duty cycle = 0.5 0.2 single pulse 0.1 0.05 0.02 1. duty cycle, d = 2. per unit base = r thja = 90 c/w 3. t jm ? t a = p dm z thja (t) 4. surface mounted t 1 t 2 p dm notes: t 1 t 2
nthc5513 http://onsemi.com 582 figure 22. basic figure 23. style 2 0.457 0.018 2.032 0.08 0.635 0.025 0.66 0.026 0.711 0.028 0.457 0.018 2.032 0.08 0.635 0.025 0.66 0.026 0.254 0.010 mm inches scale 20:1 1.092 0.043 0.178 0.007 basic pad patterns the basic pad layout with dimensions is shown in figure 22. this is sufficient for low power dissipation mosfet applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. the minimum recommended pad pattern shown in figure 23 improves the thermal area of the drain connections (pins 5, 6, 7, 8) while remaining within the confines of the basic footprint. the drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). this will assist the power dissipation path away from the device (through the copper lead ? frame) and into the board and exterior chassis (if applicable) for the single device. the addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.
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